I'm a software engineer at Arista Networks, in Santa Clara, CA working on firewalls, specifically writing drivers and implementing features using the PMF (Programmable Mapping and Filtering) block and TCAM (Ternary Content-Addressable Memory) in Broadcom network ASIC's.
In my free time, I like messing around with compilers and computer graphics.
Arista Networks, Software Engineer - May 2018...Present
- User-space Broadcom ASIC drivers for TCAM ACL features.
- Ported CPU firewall to Jericho2 (400G) chip.
- Added best-effort resource allocation for BGP Flowspec.
- Fixed performance regressions in BGP Flowspec.
- Python, C++, GDB, perf, Linux, Networking
Mentor Graphics, Software Intern - May 2017...Aug 2017
- Printed circuit board (PCB) design file importer bug fixes.
- Implemented concave polygon intersection.
- Identified unsynchronized multithreaded std::vector mutation.
- Fixed stack overrun from switching thread library.
- C++, GDB, Windows, Linux, Computer Graphics
Seagate Technology, Software Intern - May 2016...Aug 2016
- Added tool to auto-generate latency heatmap for read/write.
- Python, Matplotlib, Data Visualization
- Mylang: A compiler (LLVM frontend) for a custom programming language in Rust.
- Cranelift: A small fix I contributed to the open source Cranelift code generator's instruction legalization.
- llvm-project: A fork of Clang that adds Python syntax to C.
University of Colorado at Boulder, B.S. Computer Science
GPA 3.887, Graduated May 2018